1. Field of the Invention
The present invention relates generally to a method for fabricating capacitor, and more particularly, to a method for fabricating capacitor capable of increasing capacitance and minimizing leakage current.
2. Description of the Related Art
As is generally known, there is a rapid increase in demand of memory devices resulting from the development of semiconductor fabrication methods. The capacitor is employed as a data storage means and the capacitance depends on electrode area, distance between electrodes and the dielectric constant of the dielectric layer interposed between electrodes. However, as semiconductor devices become highly integrated, the capacitor formation region and the electrode area of capacitor are decreased, thereby reducing capacitance.
Therefore, methods have been proposed to deposit a ruthenium (Ru) layer as a storage node electrode in Metal-Insulator-Metal (MIM) capacitors and a high dielectric TaON layer is deposited thereon and then, a metal layer is deposited on the dielectric layer, thereby maximizing the capacitance of the TaON capacitor.
FIGS. 1A to 1I are cross sectional views showing the steps of a conventional method for fabricating a capacitor.
Referring to FIG. 1A, a first insulating layer 104 is deposited with oxidized silicon on a semiconductor substrate 100, including over a conductive region 102, such as a source/drain, and then, the first insulating layer 104 is etched to expose the conductive region 102 in accordance with a photolithography process, thereby forming a first opening 106 as a storage node contact.
Referring to FIG. 1B, a polycrystalline silicon layer is deposited to cover the first opening 106 on the substrate 100, including over the first insulating layer 104 and then, an etch process is performed on the polycrystalline silicon layer to form a conductive plug 108. The conductive plug 108 is formed in the first opening 106 to a depth sunken from the top surface of the first insulating layer 104, as shown.
Referring to FIG. 1C, a Ti layer and a TiN layer are sequentially formed on the substrate 100 having the conductive plug 108 in accordance with known sputtering methods and then, etch back processes are performed on the Ti layer and the TiN layer to form a barrier metal layer a1, comprising layers 110,112, respectively.
Referring to FIG. 1D, a second insulating layer 121 is deposited on the resulting structure and then, the second insulating layer 121 is etched in accordance with a photolithography process, thereby forming a second opening 122 to which a part corresponding to the barrier metal layer a1 is exposed.
Referring to FIG. 1E, a first ruthenium (Ru) layer 140 for storage node electrode formation is deposited to cover the second opening 122 on the second insulating layer 121 in accordance with a Physical Vapor Deposition (PVD) process. The deposition of the first ruthenium (Ru) layer 140 is performed in a conventional CVD chamber (not shown).
Referring to FIG. 1F, a second ruthenium (Ru) layer is deposited on the first ruthenium (Ru) layer 140 in accordance with a Chemical Vapor Deposition (CVD) process, thereby obtaining a ruthenium (Ru) layer 142 having a desirable thickness. The deposition of the second ruthenium (Ru) layer is performed in a conventional CVD chamber (not shown) by transferring the substrate having deposited thereon the first ruthenium (Ru) layer 140 from the PVD chamber.
When the ruthenium (Ru) layer is deposited only in accordance with the CVD method, although the deposition speed is decreased on the surface of the first insulating layer, the quality of ruthenium Ru layer deteriorates. Therefore, the ruthenium (Ru) layer 142 for storage node electrode formation of a capacitor is formed by depositing the first ruthenium (Ru) layer 140 in accordance with the PVD process and then, depositing the second ruthenium (Ru) layer on the first ruthenium (Ru) layer 140 in accordance with the CVD process.
Referring to FIG. 1G, etch back processes are performed on the ruthenium (Ru) layer to expose the second insulating pattern 121, thereby forming a storage electrode 143 of the capacitor. Then, the second insulating pattern 121 is removed.
Referring to FIG. 1H, a dielectric layer 126 is formed to cover the storage electrode 143 of the capacitor and then, a plate electrode 130 of the capacitor is formed over the dielectric layer 126, as shown in FIG. 1I. Here, the dielectric layer 126 preferably is a TiON layer having a high dielectric constant and the plate electrode 130 is a ruthenium (Ru) layer formed by both PECVD and LPCVD processes, as is employed in the formation of the storage node electrode 143. Alternatively, instead of the ruthenium (Ru) layer, a TiN layer may be employed as the plate electrode 130.
However, according to the conventional method, both PVD and CVD processes are performed, respectively, during the steps for deposition of the ruthenium (Ru) layer for storage node electrode formation. Therefore, there is a problem in that extra process steps must be performed, such as transfer from the PVD chamber to the CVD chamber.
Therefore, the present invention has been made to solve the above-mentioned problems and the object of the present invention is to provide a method for fabricating a method for capacitor fabrication capable of simplifying formation processes of the ruthenium (Ru) layer for the storage node electrode formation of the capacitor.
In order to accomplish the above object, the present invention comprises the steps of: forming a first insulating layer having a first opening exposing a predetermined region; forming a conductive plug filled within the first opening; forming a second insulating layer having a second opening exposing the conductive plug on the first insulating layer; forming a conductive layer covering the second opening on the second insulating layer by sequentially performing PECVD and LPCVD processes; exposing the second insulating layer by performing etch back on the conductive layer; forming a storage node electrode of the capacitor by removing the second insulating layer; forming a dielectric layer covering the storage node electrode and forming a plate electrode.
Another alternative embodiment of the present invention comprises the steps of: forming a first insulating layer having a first opening exposing a predetermined region on a substrate; forming a conductive plug filled within the first opening; forming a second insulating layer having a second opening exposing the conductive plug on the first insulating layer; forming a conductive layer covering the second opening by sequentially performing PECVD and LPCVD processes on the second insulating layer; performing a first thermal treatment on the conductive layer under an atmosphere of N2 gas; exposing the second insulating layer by performing etch back processes on the resulting conductive layer; forming a storage node electrode of the capacitor by removing the second insulating layer; forming a dielectric layer covering the storage node electrode; and forming a plate electrode covering the dielectric layer.